 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ams datasheet, confidential: 2013-aug [1-02] AS3709 C 1 AS3709 pmic with 5 dcdc and 2 ldos the AS3709 is an ultra compact pmic containing 5 high-efficiency, constant-frequency synchronous buck converters in addition with two universal io ldos are available for lower current power rails. the wide input voltage range (2.7v to 5.5v), automatic power-save mode and minimal external component requirements make the AS3709 perfect for any single li-ion battery-powered or fixed 3.3v/5v supply application. typical supply current with no load is 110a and decreases to 7a in shutdown mode. an internal synchronous switch increases efficiency and eliminates the need for an external schottky diode. the internally fixed switching frequency (2mhz, 3mhz or 4mhz) allows the use of small surface mount external components. very low output voltages can be delivered with the internal 0.6v feedback reference voltage. the AS3709 is available in a 32-p in qfn 4x4mm package and in a very compact csp36 with 0.4mm pitch. for further understanding in regards to the contents of the datasheet, please refer to the reference guide located at the end of the document. key benefits & features the benefits and features of AS3709, pmic with 5 dcdc and 2 ldos are listed below: figure 1: added value of using AS3709 benefits features compact design due to small coils for io and memory voltage generation 5 dcdc step down regulators (2-4mhz) independent voltage rails for general purpose io supplies 2 universal io ldos flexible and fast adaptation to different processors/applications otp programmable boot and power-down sequence power saving control according to the processors needs. stand-by function with pr ogrammable sequence and voltages self-contained start-up and control for single-cell battery applications. safety shutdown feature. control interface i2c/spi control lines on key with 4/8s emergency shut-down por with reset i/o dedicated packages for specific applications. optimization for pcb cost or size. 32-pin qfn (4x4mm), 0.4mm pitch 36-ball wl-csp 0.4mm pitch general description
AS3709 C 2 ams datasheet, confidential: 2013-aug [1-02] applications the device is ideal for: ? ssds, mobile communication devices ?laptops and pdas ? ultra-low-power systems ? medical instruments or any other space-limited application with low power-consumption requirements. block diagram the functional blocks of this device for reference are shown below: figure 2: AS3709 block diagram gpios dcdc1 0.7 ? 1a 0.6 ? 3.35v 2 ? 4mhz ldo1 pmos 0.6 0.8 ? 3.3v 300ma i2c system control & reference supervisor (supply & temp) por boot rom otp AS3709 ldo2 pmos 0.6 0.8 ? 3.3v 300ma sclk on xres v2_5 vssa gpio1 ldo1 vin_ldo2 ldo2 vss_ldo2 vsup_sd1 lx_sd1 fb_sd1 pvss_sd1 2.2uf 1uh 1uf 10uf dcdc2 0.7 ? 1a 0.6 ? 3.35v 2 ? 4mhz vsup_sd2 lx_sd2 fb_sd2 pvss_sd2 2.2uf 1uh 10uf dcdc3 0.7 ? 1a 0.6 ? 3.35v 2 ? 4mhz vsup_sd3 lx_sd3 fb_sd3 pvss_sd3 2.2uf 1uh 10uf dcdc4 0.7 ? 1a 0.6 ? 3.35v 2 ? 4mhz vsup_sd4 lx_sd4 fb_sd4 pvss_sd4 2.2uf 1uh 10uf dcdc5 0.7 ? 1a 0.6 ? 3.35v 2 ? 4mhz vsup_sd5 lx_sd5 fb_sd5 pvss_sd5 2.2uf 1uh 10uf vsup vsup vsup vsup vsup sd1 sd2 sd3 sd4 sd5 gpio2 sda 2.2uf 2.2uf vin_ldo1 vss_ldo1 2.2uf 2.2uf vsup vsup ams datasheet, confidential: 2013-aug [1-02] AS3709 C 3 pin assignment t he AS3709 pin assignme nts are described below. figure 3: 36 balls wl-csp with 0.4mm pitch figure 4: 32 pins qfn 4x4 with 0.4mm pitch ball assignments: shows the top view ball assignment of the AS3709 wl-csp. pin assignment: shows the top view pin assignment of the AS3709 qfn package. pin assignment a2 xres a3 gpio2 c1 vsup sd1 d2 pvss sd1 c2 lx_sd1 b3 on a4 vssa b2 sda b1 v2_5 c4 gpio1 d3 ldo1 a1 scl b4 fb_sd5 c3 fb_sd1 d4 ldo2 pin a1 indicator a5 pvss sd5 b5 lx_sd5 c6 lx_sd4 d5 pvss sd4 b6 vsup sd5 c5 fb_sd4 e1 vsup sd2 f2 pvss sd2 e2 lx_sd2 e4 fb_sd3 f3 vin ldo1 e3 fb_sd2 f4 vin ldo2 e6 vsup sd3 f5 pvss sd3 e5 lx_sd3 1 3 5 7 AS3709 qfn 32-pin 4x4mm exposed pad: gnd vsup_sd1 scl lx_sd5 vsup_sd4 pvss_sd4 vsup_sd3 pvss_sd1 vsup_sd2 24 22 20 18 lx_sd1 v2_5 fb_sd1 lx_sd2 23 21 19 17 2 4 6 8 vsup_sd5 lx_sd4 fb_sd4 lx_sd3 28 gpio2 27 xres 26 on 25 sda 32 pvss_sd5 31 fb_sd5 30 vssa 29 gpio1 12 ldo2 11 vin_ldo2 10 fb_sd3 9 pvss_sd3 16 pvss_sd2 15 fb_sd2 14 vin_ldo1 13 ldo1 33 AS3709 C 4 ams datasheet, confidential: 2013-aug [1-02] pin assignment figure 5: pin description pin number pin name pin type description if not used qfn wlp 1 b5 lx_sd5 dig out dcdc sd5 switch output to coil open 2 b6 vsup_sd5 sup in dcdc sd5 pos supply terminal always needed 3 b6 vsup_sd4 sup in dcdc sd4 pos supply terminal always needed 4 c6 lx_sd4 dig out dcdc sd4 switch output to coil open 5 d5 pvss_sd4 gnd dcdc sd4 neg supply terminal always needed 6 c5 fb_sd4 ana in dcdc sd4 feedback pin open 7 e6 vsup_sd3 sup in dcdc sd3 pos supply terminal always needed 8 e5 lx_sd3 dig out dcdc sd3 switch output to coil open 9 f5 pvss_sd3 gnd dcdc sd3 neg supply terminal always needed 10 e4 fb_sd3 ana in dcdc sd3 feedback pin open 11 f4 vin_ldo2 sup in supply pin for ldo2 always needed 12 d4 ldo2 ana out output voltage of ldo2 open 13 d3 ldo1 ana out output voltage of ldo1 open 14 f3 vin_ldo1 sup in supply pin for ldo1 always needed 15 e3 fb_sd2 ana in dcdc sd2 feedback pin open 16 f2 pvss_sd2 gnd dcdc sd2 neg supply terminal always needed 17 e2 lx_sd2 dig out dcdc sd2 switch output to coil open 18 e1 vsup_sd2 sup in dcdc sd2 pos supply terminal always needed 19 c3 fb_sd1 ana in dcdc sd1 feedback pin open 20 d2 pvss_sd1 gnd dcdc sd1 neg supply terminal always needed 21 c2 lx_sd1 dig out dcdc sd1 switch output to coil open 22 c1 vsup_sd1 sup in dcdc sd1 pos supply terminal always needed 23 b1 v2_5 ana out internal 2.5v regulator output always needed 24 a1 scl dig in 2-wire serial if clock input open 25 b2 sda dig io 2-wire serial if data io open 26 b3 on dig in power up input open 27 a2 xres dig io reset io, external pull-up resistor needed always needed ams datasheet, confidential: 2013-aug [1-02] AS3709 C 5 pin assignment 28 a3 gpio2 ana io general purpose io 2 open 29 c4 gpio1 ana io general purpose io 1 open 30 a4 vssa gnd gnd reference for analog blocks always needed 31 b4 fb_sd5 ana in dcdc sd5 feedback pin open 32 a5 pvss_sd5 gnd dcdc sd5 neg supply terminal always needed 33 vss gnd exposed pad always needed pin number pin name pin type description if not used qfn wlp AS3709 C 6 ams datasheet, confidential: 2013-aug [1-02] absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated under operating conditions is not im plied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. figure 6: absolute maximum ratings symbol parameter min max units comments electrical parameters supply voltage to ground 5v pins -0.5 7.0 v applicable for pins: vsup_sdx, vin_ldox, sclk, sda, on, xres, gpiox, lx_sdx supply voltage to ground 3v pins -0.5 5.0 v applicable for pins: v2_5, ldox, fb_sdx voltage difference between ground terminals -0.3 0.3 v applicable for pins: vssa, pvss_sdx, exposed pad input current (latch-up immunity) -100 100 ma norm: jedec jesd78 continuous power dissipation (t a = +70c) p t continuous power dissipation 1.2 w p t (1) for qfn32 package (r thja ~ 45k/w) 1.1 w p t (1) for wl-csp36 package (rthja ~ 50k/w) electrostatic discharge v esd-hbm electrostatic discharge hbm 2 kv norm: jedec jesd22-a114f temperature ranges and storage conditions t amb operating temperature -40 +85 c t j junction temperature +125 c storage temperature range -55 +150 c qfn storage temperature range -55 +125 c wl-csp humidity non-condensing 85 % absolute maximum ratings ams datasheet, confidential: 2013-aug [1-02] AS3709 C 7 absolute maximum ratings note(s) and/or footnote(s): 1. depending on actual pcb layout and pcb used. 2. the reflow peak soldering temperature (body temperature) is specified according ipc/jedec j-std-020 moisture/reflow sensiti vity classification for non hermetic solid state surface mount devices temperature (soldering) t body package body temperature +260 c 32-pin qfn: norm ipc/jedec j-std-020 (2) the lead finish for pb-free leaded packages is matte tin (100% sn) t body package body temperature +260 c 36-ball wl-csp: norm ipc/jedec j-std-020 (2) msl qfn moisture sensitive level 3 represents a maximum floor life time of 168h msl wl-csp moisture sensitive level 1 represents an unlimited floor life time symbol parameter min max units comments AS3709 C 8 ams datasheet, confidential: 2013-aug [1-02] electrical characteristics all limits are guaranteed. the parameters with min and max values are guaranteed with production tests or sqc (statistical quality control) methods. figure 7: electrical characteristics electrical characteristics: v sup = 3.7v, v out < v in C 0.5v, t amb = -40c to +85c, typ. values @ t amb = +25c (unless otherwise specified) symbol parameter conditions min typ max unit v in input voltage range pin v sup 2.7 5.5 v i q quiescent current normal operating current. with bit low_power_on = 0; only v2_5 active 155 200 a i lowpower low-power quiescent current normal operating current. with bit low_power_on = 1; only v2_5 active 110 i poweroff shutdown current with bit power_off = 1; only v2_5 is active in power off mode. not tested, guaranteed by design 720 electrical characteristics ams datasheet, confidential: 2013-aug [1-02] AS3709 C 9 detailed description - power management functions step down dcdc converter the step-down converter is a high-efficiency fixed frequency current mode regulator. by using low resistance internal pmos and nmos switches, efficiency up to 95% can be achieved. the fast switching frequency allows using small inductors, without increasing the current ripple. the unique feedback and regulation circuit guarantees op timum load and line regulation over the whole output voltage range, up to an output current of 1a, with an output capacitor of only 10f. the implemented current limitation protects the dcdc converter and the coil during overload condition. figure 8: step down dc/dc converter block diagram detailed description - power management functions logic + - + - + - s i min i limit 250ma 1.2a i sensep i sensen zero comparator pwm comparator overvoltage comparator ref + 8% ref - 5% slope compensation softstart ref = 0.6v skip sd_low_noise clk sd_lv buck_v fb_sd vss_sd lx_sd vout vsup + - - + + - 2.2uf 1uh 10uf AS3709 C 10 ams datasheet, confidential: 2013-aug [1-02] detailed description - power management functions mode settings to allow optimized performance in different applications, there are bit settings possible, to get the best compromise between high efficiency and low input/output ripple. low-ripple, low-noise operation low-ripple, low-noise operation can be enabled by setting bit sd_low_noise = 1. in this mode there is no minimu m coil current necessary before switching off the pmos. as long as the load current is superior to the ripple current, the device operates in continuous mode. when the load current gets lower, the discontinuous mode is triggered. resultant the auto-z ero comparator stops the nmos conduction to avoid load disc harger and the duty cycle is reduced down to t min_on to keep the regulation loop stable. this results in a very low ri pple and noise, but decreased efficiency at light loads, especially at low input to output voltage differences. only in the case the load curren t gets so small, that less than the minimum on time of the pmos would be needed to keep the loop in regulation, the regulator will enter low power mode operation. the crossover point is about 15ma for v in = 3v, v out = 1.2v, 1h, 4mhz. figure 9: dc/dc buck low noise mode high-efficiency operation (default setting) high-efficiency operation is enabled by setting bit sd_low_noise = 0. in this mode there is a minimu m coil current necessary before switching off the pmos. resultant there are less pulses dc/dc buck burst mode: shows the dc/dc switching waveforms for low noise operation. vout (50mv/div) lx (2v/div) coil current (200ma/div) time (5us/div) ams datasheet, confidential: 2013-aug [1-02] AS3709 C 11 detailed description - power management functions necessary at low output loads, and therefore the efficiency increases. as drawback, this mode increases the ripple up to a higher output current. the crossover point to low power mode is already reached at reasonable high output currents. (e.g. @110ma for v in = 3v, v out = 1.2v, 1h, 4mhz) figure 10: dc/dc buck high efficiency mode low power mode operation (automatically controlled) as soon as the output voltage stays above the desired target value for a certain time, some internal blocks will be powered down leaving the output floating to lower the power consumption. normal operation starts as soon as the output drops below the target value for a similar amount of time. to minimize the accuracy error some internal circuits are kept powered to assure a minimized output voltage ripple. two addition guard bands, based on comparators, are set at 5% of the target value to react quickly on large over/undershoots by immediately turning on the output drivers without the normal ti me delays. this ensures a minimized ripple also in very extreme load conditions. dvm (dynamic voltage management) to minimize the over-/undersho ot during a change of the output voltage, the dvm can be enabled. with dvm the output voltage will ramp up/down with a selectable slope after the new value was written to the registers. without dvm the slew rate of the output voltage is only determined by external components like the coil and load capacitor as well as the load current. dvm can be selected for all step-down converters, but only for one at a time. (see sd_dvm_select and dvm_time description) dc/dc buck burst mode: shows the dc/dc switching waveforms for high efficiency operation vout (50mv/div) lx (2v/div) coil current (200ma/div) time (20us/div) AS3709 C 12 ams datasheet, confidential: 2013-aug [1-02] detailed description - power management functions fast regulation mode this mode can be used to react faster on sudden load changes and thus minimize the over-/unde rshoot of the output voltage. this mode needs a 22uf output capacitor instead the 10uf one to guarantee the stability of the regulator. the mode is enabled by setting sd_fast =1. selectable frequency operation especially for very low load conditions, e.g. during a sleep mode of a processor, the switching frequency can be reduced to achieve a higher efficiency. the frequency can be set to 2, 3 or 4mhz and this mode is selected by setting sd_freq and sd_fsel to the appropriate values. 100% pmos on mode for low dropout regulation for low input to output voltage difference the dcdc converter can use 100% duty cycle for the pmos transistor, which is then in ldo mode. step down converter configuration modes the step down dc/dc converters have two configuration modes to deliver different output currents for the applications. the operating mode is selected by setting the bit sd2_slave , sd4_slave and sd5_slave (the default is set by the boot-otp). figure 11: dcdc step down normal operating mode normal operating mode: sd2_slave = 0, sd4_slave = 0, sd5_slave = 0 dcdc step down 3 vsup_sd3 lx_ sd3 fb_sd3 pvss_sd3 2.2uf 1uh 10 uf vsup dcdc step down 4 vsup_sd4 lx_ sd4 fb_sd4 pvss_sd4 2.2uf 1uh 10 uf vsup dcdc step down 5 vsup_sd5 lx_ sd5 fb_sd5 pvss_sd5 2.2uf 1uh 10 uf vsup dcdc step down 1 vsup_sd1 lx_ sd1 fb_sd1 pvss_sd1 vsup 10uf 2.2 uf sd1 0.6 ? 3 .3 v 0.7 ? 1a 1uh dcdc step down 2 vsup_sd2 lx_ sd2 fb_sd2 pvss_sd2 vsup 10uf 2.2 uf 1uh 5 x 1a sd2 0.6 ? 3 .3 v 0.7 ? 1a sd3 0.6 ? 3 . 3v 0.7 ? 1 a sd4 0.6 ? 3 . 3v 0.7 ? 1 a sd5 0.6 ? 3 . 3v 0.7 ? 1 a ams datasheet, confidential: 2013-aug [1-02] AS3709 C 13 detailed description - power management functions figure 12: dcdc step down sd3/sd4 operating mode sd3/sd4 operating mode: sd2_slave = 0, sd4_slave = 1, sd5_slave = 0 figure 13: dcdc step down sd1/sd2 & sd3/sd4 operating mode sd3/sd4 & sd4/sd5 operating mode: sd2_slave = 1, sd4_slave = 1, sd5_slave = 0 dcdc step down 3 vsup_sd3 lx_ sd3 fb_sd3 pvss_sd3 2.2 uf 1uh 10uf vsup dcdc step down 4 vsup_sd4 lx_ sd4 fb_sd4 pvss_sd4 2 .2uf vsup dcdc step down 5 vsup_sd5 lx_ sd5 fb_sd5 pvss_sd5 2.2uf 1uh 10 uf vsup dcdc step down 1 vsup_sd1 lx_ sd1 fb_sd1 pvss_sd1 vsup 10 uf 2.2 uf 1uh dcdc step down 2 vsup_sd2 lx_ sd2 fb_sd2 pvss_sd2 vsup 10 uf 2.2 uf 1uh 3 x 1a 1 x 2a sd1 0. 6 ? 3 .3 v 0.7 ? 1a sd2 0. 6 ? 3 .3 v 0.7 ? 1a sd 3 0.6 ? 3.3v 1.4 ? 2a sd5 0. 6 ? 3 . 3v 0. 7 ? 1 a 10 uf dcdc step down 3 vsup_sd3 lx_ sd3 fb_sd3 pvss_ sd3 2.2 uf 1uh 10uf vsup dcdc step down 4 vsup_sd4 lx_ sd4 fb_sd4 pvss_ sd4 2 .2uf vsup dcdc step down 5 vsup_sd5 lx_ sd5 fb_sd5 pvss_ sd5 2 .2uf 1uh 10 uf vsup dcdc step down 1 vsup_sd1 lx_ sd1 fb_sd1 pvss_sd1 vsup 10uf 2. 2uf 1uh dcdc step down 2 vsup_sd2 lx_ sd2 fb_sd2 pvss_sd2 vsup 10 uf 2.2uf 1 x 1a 2 x 2a sd1 0. 6 ? 3 .3 v 1.4 ? 2a sd 3 0.6 ? 3.3v 1.4 ? 2a sd5 0.6 ? 3 .3v 0.7 ? 1 a 10 uf AS3709 C 14 ams datasheet, confidential: 2013-aug [1-02] detailed description - power management functions figure 14: dcdc step down sd3/sd4/sd5 operating mode sd3/sd4/sd5 operating mode: sd2_slave = 0, sd4_slave = 1, sd5_slave = 1 figure 15: dcdc step down sd1/sd2 & sd3/sd4/sd5 operating sd1/sd2 & sd3/sd4/sd5 operating mode: sd2_slave = 1, sd4_slave = 1, sd5_slave = 1 dcdc step down 3 vsup_sd3 lx_ sd3 fb_sd3 pvss_sd3 2.2 uf 1uh 10uf vsup dcdc step down 4 vsup_sd4 lx_ sd4 fb_sd4 pvss_sd4 2 .2uf vsup dcdc step down 5 vsup_sd5 lx_ sd5 fb_sd5 pvss_sd5 dcdc step down 1 vsup_sd1 lx_ sd1 fb_sd1 pvss_sd1 vsup 10 uf 2.2 uf 1uh dcdc step down 2 vsup_sd2 lx_ sd2 fb_sd2 pvss_sd2 vsup 10 uf 2.2 uf 1uh 2 x 1a 1 x 3a sd1 0. 6 ? 3 .3 v 0.7 ? 1a sd2 0. 6 ? 3 .3 v 0.7 ? 1a sd 3 0.6 ? 3.3v 2.1 ? 3a 22 uf 2.2uf vsup dcdc step down 3 vsup_sd3 lx_ sd3 fb_sd3 pvss_ sd3 2.2 uf 1uh 10uf vsup dcdc step down 4 vsup_sd4 lx_ sd4 fb_sd4 pvss_ sd4 2 .2uf vsup dcdc step down 5 vsup_sd5 lx_ sd5 fb_sd5 pvss_ sd5 dcdc step down 1 dcdc step down 2 1 x 2a 1 x 3a sd 3 0.6 ? 3.3v 2.1 ? 3a 22 uf 2.2uf vsup vsup_sd1 lx_ sd1 fb_sd1 pvss_sd1 vsup 10uf 2. 2uf 1uh vsup_sd2 lx_ sd2 fb_sd2 pvss_sd2 vsup 10 uf 2.2uf sd1 0. 6 ? 3 .3 v 1.4 ? 2a ams datasheet, confidential: 2013-aug [1-02] AS3709 C 15 detailed description - power management functions parameters figure 16: step down dcdc converter electrical characteristics figure 17: step down dcdc external components symbol parameter conditions min typ max unit v in input voltage pin v sup 2.7 5.5 v v out regulated output voltage 0.6125 3.35 v v out_tol output voltage tolerance min. 40mv -3 +3 % i limit current limit 1.2 a r pmos p-switch on resistance 0.25 0.5 r nmos n-switch on resistance 0.25 0.5 f sw switching frequency sdx_frequ = 1 sdx_fsel = 1 fclk_int = 4mhz 4mhz sdx_frequ = 1 sdx_fsel = 0 fclk_int = 4mhz 3mhz sdx_frequ = 0 sdx_fsel = 0 fclk_int = 4mhz 2mhz i load load current v out 1.8v 01 a v out > 1.8v 00.7 i sup_dcdc current consumption operating current without load 60 a shutdown current 0.1 t min_on minimum on time 40 ns eff efficiency see figures below % symbol parameter conditions min typ max unit c fb_sdx output capacitor ceramic x5r or x7r 8 10 f c vsup_sdx input capacitor ceramic x5r or x7r 2.2 f AS3709 C 16 ams datasheet, confidential: 2013-aug [1-02] detailed description - power management functions figure 18: dcdc sd1 efficiency vs. output current sd1 efficiency vs. output current: v in = 3.7v, 3mhz operation, xfl4020 1uh coil, t a = +25c figure 19: dcdc sd1 efficiency vs. output current sd1 efficiency vs. output current: v in = 3.0v, 3mhz operation, xfl4020 1 h coil, t a = +25c l sdx inductor 4mhz operation 1 h 3mhz operation 1 2mhz operation 2.2 symbol parameter conditions min typ max unit 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 10 efficiency (%) output current (a) vout = 1.0v vout = 1.0v, low noise vout = 1.8v vout = 1.8v, low noise vout = 3.0v vout = 3.0v, low noise 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 10 efficiency (%) output current (a) vout = 1.2v vout = 1.2v, low noise vout = 2.5v vout = 2.5v, low noise 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 10 efficiency (%) output current (a) vout = 1.0v vout = 1.0v, low noise vout = 1.8v vout = 1.8v, low noise 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 10 efficiency (%) output current (a) vout = 1.2v vout = 1.2v, low noise vout = 2.5v vout = 2.5v, low noise ams datasheet, confidential: 2013-aug [1-02] AS3709 C 17 detailed description - power management functions figure 20: dcdc sd1 efficiency vs. output current sd1 efficiency vs. output current: v in = 3.7v, v out = 1.2v/2.5v, 3mhz operation, t a = +25c figure 21: dcdc sd1 + sd2 efficiency vs. output current sd1 + sd2 efficiency vs. output current: v in = 3.7v, 3mhz operation, xfl4020 1 h coil, t a = +25c 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 efficiency (%) output current (a) 1uh xfl4020, 11m ? , 1.2v 1uh xfl4020, 11m ? , ln, 1.2v 1uh lqm2hp_g0, 55m ? , 1.2v 1uh lqm2hp_g0, 55m ? , ln, 1.2v 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 efficiency (%) output current (a) 1uh xfl4020, 11m ? , 2.5v 1uh xfl4020, 11m ? , ln, 2.5v 1uh lqm2hp_g0, 55m ? , 2.5v 1uh lqm2hp_g0, 55m ? , ln, 2.5v 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 10 efficiency (%) output current (a) vout = 1.0v vout = 1.0v, low noise vout = 1.8v vout = 1.8v, low noise vout = 3.0v vout = 3.0v, low noise 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 10 efficiency (%) output current (a) vout = 1.2v vout = 1.2v, low noise vout = 2.5v vout = 2.5v, low noise AS3709 C 18 ams datasheet, confidential: 2013-aug [1-02] detailed description - power management functions figure 22: dcdc sd1 + sd2 efficiency vs. output current sd1 + sd2 efficiency vs. output current: v in = 3.0v, 3mhz operation, xfl4020 1 h coil, t a = +25c figure 23: dcdc sd1 + sd2 efficiency vs. output current sd1 + sd2 efficiency vs. output current: v in = 3.7v, v out = 1.2v, 3mhz operation, t a = +25c 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 10 efficiency (%) output current (a) vout = 1.0v vout = 1.0v, low noise vout = 1.8v vout = 1.8v, low noise 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 10 efficiency (%) output current (a) vout = 1.2v vout = 1.2v, low noise vout = 2.5v vout = 2.5v, low noise 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 10 efficiency (%) output current (a) 1uh xfl4020 1uh xfl4020, low noise 0.6uh xal4020 0.6uh xal4020, low noise 1uh lqm2hp_g0 1uh lqm2hp_g0, low noise ams datasheet, confidential: 2013-aug [1-02] AS3709 C 19 detailed description - power management functions figure 24: dcdc sd3 + sd4 + sd5 efficiency vs. output current sd3 + sd4 + sd5 efficiency vs. output current: v in = 3.7v, 3mhz operation, xfl4020 1 h coil, t a = +25c figure 25: dcdc sd3 + sd4 + sd5 efficiency vs. output current sd3 + sd4 + sd5 efficiency vs. output current: v in = 3.0v, 3mhz operation, xfl4020 1 h coil, t a = +25c 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 10 efficiency (%) output current (a) vout = 1.0v vout = 1.0v, low noise vout = 1.8v vout = 1.8v, low noise vout = 3.0v vout = 3.0v, low noise 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 10 efficiency (%) output current (a) vout = 1.2v vout = 1.2v, low noise vout = 2.5v vout = 2.5v, low noise 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 10 efficiency (%) output current (a) vout = 1.0v vout = 1.0v, low noise vout = 1.8v vout = 1.8v, low noise 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 10 efficiency (%) output current (a) vout = 1.2v vout = 1.2v, low noise vout = 2.5v vout = 2.5v, low noise AS3709 C 20 ams datasheet, confidential: 2013-aug [1-02] detailed description - power management functions figure 26: dcdc sd3 + sd4 + sd5 efficiency vs. output current figure 27: dcdc sd3 + sd4 + sd5 efficiency vs. output current sd3 + sd4 + sd5 efficiency vs. output current: v in = 3.7v, v out = 1.2v, 3mhz operation, t a = +25c sd3 + sd4 + sd5 efficiency vs. output current: v in = 3.7v, v out = 1.2v, xfl4020 1 h coil, t a = +25c 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 10 efficiency (%) output current (a) 1uh xfl4020, 11m ? 1uh xfl4020, ln, 11m ? 0.6uh xal4020, 9m ? 0.6uh xal4020, ln, 9m ? 40 45 50 55 60 65 70 75 80 85 90 95 100 0,001 0,01 0,1 1 10 efficiency (%) output current (a) 2mhz 3mhz 4mhz ams datasheet, confidential: 2013-aug [1-02] AS3709 C 21 detailed description - power management functions universal io ldo regulators 2 universal io range ldos offer a wide input (1.8v to 5.5v) as well as a wide output (0.8 to 3. 3v) voltage range to be used for general purpose peripheral su pply. up to 300ma possible output currents are offered with good noise and regulation performance and very low quiescent current even suitable for stand-by power supply. figure 28: universal io ldo block diagram AS3709 ldo: shows the detailed universal io ldo block diagram + - vin_ldox ldox error amplifier vref 2.2uf 2.2uf pmos power device vss_ldox AS3709 C 22 ams datasheet, confidential: 2013-aug [1-02] detailed description - power management functions parameter figure 29: universal io ldo electrical characteristics note: guaranteed by design and verified by laboratory ev aluation and characterization; not production tested symbol parameter note min typ max unit v in input voltage range pin vin_ldox 1.75 5.5 v v out_tol output voltage tolerance min. 40mv -3 +3 % v out output voltage range pin ldox i out < 150ma, 25mv steps 0.825 3.3 v i out_l output current (note:) ldox_ilimit = 0 (150ma) 0150ma i limit_l current limit (note:) 300 ma i out_h output current (note:) ldox_ilimit = 1 (300ma) 0300ma i limit_h current limit (note:) 500 ma r on on resistance ldo1, ldo2 0.6 psrr power supply rejection ratio f=1khz 60 db f=100khz 30 i off shut down current 100 na i q quiescent current without load 30 43 a t start startup time low current used during start-up 500 us v lnr line regulation static 0.07 %/v transient; slope: tr=15s; delta 1v 20 mv v ldr load regulation static 0.014 %/m a transient; slope: tr=15s; 1ma -> 300ma 30 mv ams datasheet, confidential: 2013-aug [1-02] AS3709 C 23 detailed description - power management functions figure 30: universal io ldo electrical characteristics low power ldo v2_5 regulator the low power ldo v2_5 is needed to supply the chip core (analog and digital) of the device. it is designed to get the lowest possible power consumption and still offering reasonable characteristics. to ensure high psrr and stability, a low-esr ceramic capacitor of min. 0.7f must be connected to the output. parameter figure 31: low power v2_5 ldo electrical characteristics figure 32: universal io ldo electrical characteristics symbol parameter note min typ max unit c out_ldox output capacitor ceramic x5r or x7r 0.7 2.2 f c vin_ldox input capacitor ceramic x5r or x7r 1 2.2 f symbol parameter note min typ max unit supply voltage range see v sup v out output voltage 2.4 2.5 2.6 v r on on resistance guaranteed by design 50 i off shut down current 100 na i q quiescent current guaranteed by design, consider chip internal load for measurements 3a t start startup time 200 s symbol parameter note min typ max unit c v2_5 output capacitor ceramic x5r or x7r 0.7 1 f AS3709 C 24 ams datasheet, confidential: 2013-aug [1-02] detailed description - system functions start-up normal start-up during a normal reset cycle (e.g. after the battery is inserted), after v2_5 is above v por and v sup is above resvoltrise a normal startup happens: ? configuration of dcdcs (combined mode or separated) is read from the boot-otp ? startup state machine read s out the internal boot-otp ? reset-timer is set by the boot-otp ? the reset is released when the reset timer expires (external pin xres) parameter figure 33: on input start-up condition symbol parameter note min typ max unit v on_il on low level voltage 0.4 v v on_ih on high level voltage 1.4 v i on_pd on pull down current 4 12 a detailed description - system functions ams datasheet, confidential: 2013-aug [1-02] AS3709 C 25 detailed description - system functions figure 34: start-up flowchart start-up vsup connected 1. v2_5 power up 2. readout rom fuse auto_off = 1 power off state v2_5 power up quiescent current < 10ua pin on debounce time=20msec y on_input = 1 n auto_off = 1 or power_off_at_vsuplow = 1 y vsup debounce state measuring vsup quiesent current ~200ua n vsup > resvoltrise for more than 5ms n n on_input = 1 n vsup < resvoltfall for more than 500ms y n y y y power_off = 1 off delay wait off_delay n reset all registers switch off regulators reset registers and reload fuses expect: pwr_off_at_vsuplow y run startup sequence regulator startup sequence gpio programming during sequence startup delay programmable reset timer regulator startup executed waiting time to release xres pin 2..160ms active state xres = 1 standby_mode_on = 1 or gpiox = 1 if gpiox_iosf = 6 off delay wait off_delay n stand-by state v2_5 power up all regulators with sdx_stby_on = 1 or ldox_stby_on = 1 enabled any interrupt applied or on_input = 1 force_reset = 1 or (xres is low if stdby_reset_disable = 0) or vsup < resvoltfall or tco_140_a = 1 n n y y remove stand-by force off of all regulators die temp > 140c ( tco_140_a = 1) y power_off = 1 or force_reset = 1 or xres is low or vsup < resvoltfall or tco_140_a = 1 or on long-press n y die temp > 110c ( tco_110_a = 1) n y n any state AS3709 C 26 ams datasheet, confidential: 2013-aug [1-02] detailed description - system functions reset xres is a low active bi-directional pin. an external pull-up to the periphery supply has to be added. during each reset cycle the following states are controlled by the AS3709: ? pin xres is forced to gnd ? normal startup with progra mmable power-on sequence and regulator voltages ? reset is active until the programmable reset timer (set by register bits res_timer<2:0> ) expires ? all registers are set to their default values after power-on, except the reset control- and status-registers reset reasons reset can be activated from 7 different sources: ?v por has been reached (v sup reached por level) ? resvoltfall was reached (v sup drops below resvoltfall) ? software forced reset ? power off mode ? external triggered through the pin xres ? over-temperature ?on-key long press voltage detection there are two types of voltage dependent resets: v por and v xres . v por monitors the voltage on v2_5 and v xres monitors the voltage on v sup . the linear regulator for v2_5 is always on and uses the voltage v sup as its source. the pin xres is only released if v2_5 is above v por and v sup is above resvoltrise. power off to put the chip into ultralow power mode, write 1 into power_off . the chip stays in power off mode until ? the external pin on is pulled high ?the v por level is touched to start a complete reset cycle the bit power_off is automatically cleared by this reset cycle. during power_off state all circuits are shut-off except the low power ldo (v2_5). thus the current consumption of AS3709 is reduced to less than 7a. the digital part is supplied by v2_5, all other circuits are turned off in this mode, including references and oscillator. except the reset control registers, all other registers are set to their default value after power-on. ams datasheet, confidential: 2013-aug [1-02] AS3709 C 27 detailed description - system functions software forced reset writing 1 into the register bit force_reset immediately starts a reset cycle. the bit force_reset is automatically cleared by this reset. external triggered reset if the pin xres is pulled from high to low by an external source (e.g. microprocessor or button) a reset cycle is started as well. over-temperature reset the reset cycle can be started by over-temperature conditions. long on-key press when applying a high level on the on input pin for 4s/8s (depending on on_reset_delay ) a reset is initiated. this is thought as a safety feature when the sw hangs up. parameter figure 35: xres input characteristics figure 36: reset levels symbol parameter note min typ max unit v xres_il reset low level voltage 0.4 v v xres_ih reset high level voltage 1.4 v symbol parameter note min typ max uni t v por overall power on reset monitor voltage on v2_5 power on reset for all internal functions 1.5 2.0 2.3 v v res_rise reset level for v sup rising monitor voltage on v sup rising level resvoltrise (1) v v res_fall reset level for v sup falling monitor voltage on v sup falling level 2.7 v if supresen = 1 only resvoltfall (2) v AS3709 C 28 ams datasheet, confidential: 2013-aug [1-02] detailed description - system functions note(s) and/or footnote(s): 1. the selection of the range and level is done via otp. its recommended to set the resvoltrise level 200mv above the resvoltf all level to have a hysteresis. 2. 2.7v is the default value, other levels can be set via sw. 3. xres signal is debounced wi th the specified mask time for rising- and falling slope of vsup 4. vres_fall is only accepted if the reset condition is longer than vres_mask. this guard time is used to avoid a complete rese t of the system in case of short drops of vsup. figure 37: resvoltrise/resvoltfall levels note: if bit reslevel_5v is 1, then the 5.0v mode is selected. v res_mas k mask time for v xres_fall duration for v sup < resvoltfall until a reset cycle is started (3) fastresen = 0 3 ms fastresen = 1 4 s mode 000 001 010 011 100 101 110 111 3.3v 2.7v 2.8v 2.9v 3.0v 3.1v 3.2v 3.3v 3.4v 5.0v 3.6v 3.7v 3.8v 3.9v 4.0v 4.1v 4.2v 4.4v symbol parameter note min typ max uni t ams datasheet, confidential: 2013-aug [1-02] AS3709 C 29 detailed description - system functions stand-by stand-by allows shutting down a part or the complete system. stand-by can be terminated by every possible interrupt or gpio of the pmu. the interrupt has to be enabled and gpio has to be configured before going to stand-by. figure 38: stand-by internal references low power mode use bit low_power_on to activate the low power mode. in this mode the on-chip voltage reference and the temperature supervision comparators are operating in pulsed mode. this reduces the quiescent current of the AS3709 by 45a (typ.). because of the pulsed function some specifications are not fulfilled in this mode (e.g. in creased noise), but still the full functionality is available. note(s): low power mode can be controlled by the serial interface. state description enter via gpio to enter stand-by mode the following settings have to be done: ? enable just these irq sources which sh ould lead to leave stand-by mode. ? make sure that irq is inactive (irq flags get cleared by register reading) ? set the gpio to input ( gpiox_mode = 0) ? set the gpio for stand-by control ( gpiox_iosf = 6) ?set regx_select to define the sequence for going into stand-by for up to 3 regulators ?set regx_voltage_stby if another voltage is needing during stand-by ? define which regulators should be kept powered during stand-by ( sdx_stby_on and ldox_stby_on ) ? activate the selected gpio enter via sw to enter stand-by mode the following settings have to be done: ? enable just these irq sources which sh ould lead to leave stand-by mode. ? make sure that irq is inactive (irq flags get cleared by register reading) ? define which regulators should be kept powered during stand-by ( sdx_stby_on and ldox_stby_on ) ? set the delay for going into stand-by after the sw command (off_delay ) ?set standby_mode_on to 1 stand-by v2_5 chip supply is kept on all other regulators are switched off dependent on the bits sdx_stby_on and ldox_stby_on xres goes active (can be disabled with standby_reset_disable ) and pwr_good goes inactive leave the chip will come out of stand-by with ? irq activation or ? gpio control (if entered via gpio) start-up sequence is provid ed defined by the boot rom. AS3709 C 30 ams datasheet, confidential: 2013-aug [1-02] detailed description - system functions figure 39: reference parameter gpio pins the device contains 2 gpio pins. each of the pins can be configured as digital input, digital input (with pull-up or pull-down), push-pull output or open drain output (with or without pull-up). when configured as output the output source can be a register bit, or the pwm generator. the polarity of the input and output signals can be inverted with the corresponding gpiox_invert bit, all further descriptions refer to normal (non-inverted) mode. figure 40: gpio block diagram gpio block diagram: shows the internal structure of the io pads symbol parameter note min typ max unit f clk accuracy of internal reference clock adjustable by serial interface register clk_int -12 f clk +12 % & & =1 & =1 gpiox_out: 0 vsup_low output: 2 pwr_good output: 7 q32k output: 8 interrupt output: 1 n/a: 10 n/a: 11 n/a: 13 gpiox_in: 0 n/a: 4 vselect input: 5 stand-by + vselect input: 6 gpio interrupt input: 3 n/a: 7 n/a: 12 n/a: 13 n/a: 15 gpiox_invert gpiox_iosf gpiox_iosf gpiox_mode = 1, 2 or 6 gpiox_mode = 1 gpiox_mode = 0, 2, 4, 5 or 6 gpiox_mode = 4 or 6 gpiox_mode = 5 300k 300k vsup gpiox ams datasheet, confidential: 2013-aug [1-02] AS3709 C 31 detailed description - system functions figure 41: gpio pin characteristics gpio pins: shows the key electrical pa rameter of the gpio pins. v sup =2.7 to 5.5v; unless otherwise mentioned. io functions normal io operation: if set to input, the logic level of the signal present at the gpiox pin can be read from gpiox_in . if the output mode is chosen, gpiox_out specifies the logic level of the gpiox pin. this mode is also used for the on/off control of the dcdc and ldos. the selection which regu lator is controlled by which gpio, is done with the gpio_ctrl_sdx or gpio_ctrl_ldox bits. the gpiox_mode should be set to input. interrupt output gpiox pin logic state is derived from the interrupt signal xint. whenever an interrupt is present the gpiox pin will be pulled high. the gpiox_mode should be set to output. vsup_low output gpiox pin will go high if v sup falls below resvoltfall and supresen = 0. the gpiox_mode should be set to output. gpio interrupt input a falling or rising edge will set the gpio_int bit. the gpiox_mode should be set to input. symbol parameter note min typ max unit v gpio_max max. voltage on gpio1/2 pins pin v sup is used as supply for the gpio pins v sup + 0.3 v v ol low level output voltage i ol =+1ma digital output +0.4 v v oh high level output voltage i oh =C1ma; digital push-pull output 0.8*v sup v v il low level input voltage digital input 0.4 v v ih high level input voltage digital input 1.4 v i leakage leakage current high impedance 10 a r pull-up pull-up resistance if enabled; v sup = 3.6v 300 k r pull-down pull-down resistance if enabled; v sup = 3.6v 300 k AS3709 C 32 ams datasheet, confidential: 2013-aug [1-02] detailed description - system functions vselect input as long as the gpiox pin is high the dcdc/ldos operate with the normal register settings. if the gpiox pin goes low the settings will change to the ones stored in regx_voltage . the gpiox_mode should be set to input. figure 42: gpio vselect modes io functions: shows the 4 different vselect modes, depending on the setting of gpiox_iosf stand-by and vselect input this mode is very similar to th e vselect mode described in the previous paragraph. in addition to switch between 2 register settings of 2 regulators the chip is set into stand-by mode when the gpiox pin goes low and wakes up again when the pin is pulled high. the gpiox_mode should be set to input. gpio1 and gpio2 may be used to control two regulators separately. figure 43: stand-by and vselect modes io functions: shows the 4 different vselect and stand-by contro l modes, depending on the setting of gpiox_iosf gpio1_iosf gpio2_iosf vselect mode <> 5 <> 5 no voltage select by gpio for regulator <> 5 5 gpio2 controls regulator selected by reg1_select and reg2_select 5 <> 5 gpio1 controls regulator selected by reg1_select and reg2_select 55 gpio1 controls regulator selected by reg1_select gpio2 controls regulator selected by reg2_select gpio1_iosf gpio2_iosf vselect mode stand-by control <> 6 <> 6 no voltage select by gpio for regulator no <> 6 6 gpio2 controls regulator selected by reg1_select and reg2_select yes 6<> 6 gpio1 controls regulator selected by reg1_select and reg2_select yes 66 gpio1 controls regulator selected by reg1_select gpio2 controls regulator selected by reg2_select yes ams datasheet, confidential: 2013-aug [1-02] AS3709 C 33 detailed description - system functions pwrgood output this signal will go high at the end of the start-up sequence. this can be used as a second reset si gnal to the processor to e.g. start oscillators. the gpiox_mode should be set to output. supervisor all step-down dcdcs have an integrated over-current protection. an over-temperature protection of the chip is also integrated which can be switched on with the serial interface signal temp_pmc_on (enabled by default; it is not recommended to disable the over-temperature protection). temperature supervision the chip has two signals for the serial interface: ov_temp_110 and ov_temp_140 . the flag ov_temp_110 is automatically reset if the overtemperature condition is removed, whereas ov_temp_140 has to be reset by the serial interface with the signal rst_ov_temp_140 . if the flag ov_temp_140 is set, an automatic reset of the complete chip is initiated. the chip will only start-up when the temperature falls below the t110 level (including hysteresis). the flag ov_temp_140 is not affected by this reset cycle allowing the software to detect the reason for this unexpected shutdown. figure 44: over-temperature protection symbol parameter min typ max unit t 110 ov_temp_110 rising threshold 95 110 125 c t 140 ov_temp_140 rising threshold 125 140 155 c t hyst ov_temp_110 and ov_temp_140 hysteresis 5 c AS3709 C 34 ams datasheet, confidential: 2013-aug [1-02] detailed description - system functions interrupt generation the interrupt controller generates an interrupt request for the host controller as soon as one or more of the bits in the interrupt 12 register are set by pulling low pin xint (xint has to be selected as a gpio output func tion). all the interrupt sources can be enabled in the interrupt mask 12 register. the interrupt 12 registers are cleared automatically after the host controller has read them. to prevent the AS3709 device from losing an interrupt event, the register that is read is captured before it is transmitted to th e host controller via the serial interface. as soon as the transm ission of the captured value is complete a logical and operation with the bit wise inverted captured value is applied to the register to clear all interrupt bits that have already been transmitted. clearing the read interrupt bits takes 2 clock cyc les, a read access to the same register before the clearing process has completed will yield a value of 0. note that an interr upt that has been present at the previous read access will be cleared as well in case it occurs again before the clearing process has completed. during a read access to one of the interrupt registers, the gpio pin (gpio output function) will be released. as soon as the transferred bits of the interrupt register have been cleared the gpio pin (gpio output function) will be pulled low in case a new interrupt has occurred in th e meantime. by doing so, the interrupt controller will work correctly with host controllers that are edge- and level-sensitive on their interrupt request input. multiple byte read access is recommended to avoid reading the interrupt 1 register over and over again in response to a new interrupt that has occurred in the same register (and thus pulling low the gpio pin) before the interrupt 2 register has been read. 2-wire-serial control interface feature list ? fast-mode capability (max. scl-frequency is 400 khz) ? 7+1-bit addressing mode ? 60h x 8-bit data register s (word address 0x00 - 0x60) ? write formats: single- byte-write, page-write ? read formats: current-addr ess-read, random-read, sequential-read ? sda input delay and scl spike filtering by integrated rc-components ams datasheet, confidential: 2013-aug [1-02] AS3709 C 35 detailed description - system functions i2c protocol figure 45: 2-wire serial symbol definition symbol definition rw note s start condition after stop r 1 bit sr repeated start r 1 bit dw device address for write r 1000 0010b (80h) dr device address for read r 1000 0011b (81h) wa word address r 8 bit a acknowledge w 1 bit n no acknowledge r 1 bit reg_data register data/write r 8 bit data (n) register data/read w 8 bit p stop condition r 1 bit wa++ increment word address internally r during acknowledge AS3709 (= slave) receive data AS3709 (= slave) transmits data AS3709 C 36 ams datasheet, confidential: 2013-aug [1-02] detailed description - system functions i2c write access byte write and page write formats are used to write data to the slave. figure 46: i2c byte write figure 47: i2c page write the transmission begins with the start condition, which is generated by the master when the bus is in idle state (the bus is free). the device-write address is followed by the word address. after the word address any number of data bytes can be sent to the slave. the word address is incremented internally, in order to write subsequent data bytes on subsequent address locations. for reading data from the slave de vice, the master has to change the transfer direction. this can be done either with a repeated start condition followed by the device-read address, or simply with a new transmission start followed by the device-read address, when the bus is in idle state. the device-read address is always followed by the 1 st register byte transmitted from the slave. in read mode any number of subsequent register bytes can be read from the slave. the word address is incremented internally. wa reg_data aa ap sdw write register wa++ wa reg_data 2 ... reg_data n aa a a ap sdw write register wa++ write register wa++ write register wa++ reg_data 1 ams datasheet, confidential: 2013-aug [1-02] AS3709 C 37 detailed description - system functions i2c read access random, sequential and current address read are used to read data from the slave. figure 48: i2c random read random read and sequential read are combined formats. the repeated start condition is used to change the direction after the data transfer from the master. the word address transfer is initiated with a start condition issued by the master while the bus is idle. the start condition is followed by the device-write address and the word address. in order to change the data direction a repeated start condition is issued on the 1st scl pulse after the acknowledge bit of the word address transfer. after the reception of the device-read address, the slave be comes the transmitter. in this state the slave transmits register data located by the previous received word address vector. the master responds to the data byte with a not-acknowledge, and issues a stop condition on the bus. figure 49: i2c sequential read sequential read is the extended form of random read, as more than one register-data bytes are transferred subsequently. in difference to the random read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. the number of data bytes transferred in one sequence is unlimited (consider the behavior wa dr data aasranp sdw read register wa++ wa dr data reg_data 2 ... reg_data n aasraa a np sdw read register wa++ read register wa++ read register wa++ AS3709 C 38 ams datasheet, confidential: 2013-aug [1-02] detailed description - system functions of the word-address counter). to terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the stop condition subsequently. figure 50: i2c current address read to keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. the bus is idle and the master issues a start condition followed by the device-read address. analogous to random read, a single byte transfer is terminated with a not-acknowledge after the 1 st register byte. analogous to sequential read an unlimited number of data bytes can be transferred, where the data byte s has to be responded with an acknowledge from the master. for termination of the transmission the master send s a not-acknowledge following the last data byte and a subsequent stop condition. i2c parameter figure 51: i2c sda/scl characteristics symbol parameter min typ max unit v il scl,sda low level input voltage 0.4 v v ih scl,sda high level input voltage 1.4 v data reg_data 2 ... reg_data n aa a np sdr read register wa++ read register wa++ read register wa++ ams datasheet, confidential: 2013-aug [1-02] AS3709 C 39 register description figure 52: register overview addr name AS3709 C 40 ams datasheet, confidential: 2013-aug [1-02] register description 26h gpioctrl_ldo - - gpio_ctrl_ldo2 <5:4> gpio_ctrl_ldo1 <3:2> gpio_ctrl_sd5 <1:0> 29h sd_control3 sd5_slave sd4_slave sd2_slave sd5_fsel sd5_fast sd5_low_nois e - 30h sd_control1 sd4_low_nois e sd3_low_nois e sd2_low_no ise sd1_low_noi se sd4_fast sd3_fast sd2_fast sd1_fast 31h sd_control2 sd_dvm_select <7:6> dvm_time <5:4> sd4_fsel sd3_fsel sd2_fsel sd1_fsel 32h supply_voltage_ monitor fastresen supresen resvoltfall <5:3> resvoltrise <2:0> 33h startup_control - reslevel_5v power_off_ at_vsuplow 34h resettimer - stby_reset_dis able auto_off off_delay <4:3> res_timer <2:0> 35h referencecontro l on_reset_del ay - clk_div2 standby_mo de_on clk_int <3:1> low_power_ on 36h resetcontrol onkey_reset reset_reason <6:3> on_input power_off force_reset 37h overtemperatur econtrol tco_140_a tco_110_a temp_test<5:4> rst_ov_temp_ 140 ov_temp_140 ov_temp_1 10 temp_pmc_ on 39h reg_standby_m od1 disable_regp d ldo2_stby_on ldo1_stby_ on sd5_stby_on sd4_stby_on sd3_stby_on sd2_stby_o n sd1_stby_on 73h regstatus - sd5_lv sd4_lv sd3_lv sd2_lv sd1_lv 74h interruptmask1 lowvsup_int_ m ovtmp_int_m onkey_int_ m sd5_lv_int_ m sd4_lv_int_m sd3_lv_int_m sd2_lv_int_ m sd1_lv_int_ m 75h interruptmask2 - gpio_restar t_int_m gpio_int_m addr name ams datasheet, confidential: 2013-aug [1-02] AS3709 C 41 register description 77h interruptstatus1 lowbat_int_i ovtmp_int_i onkey_int_i sd5_lv_int_i sd4_lv_int_i sd3_lv_int_i sd2_lv_int_i sd1_lv_int_i 78h interruptstatus2 - gpio_restar t_int_i gpio_int_i 90h asic_id1 asic_id1<7:0> 91h asic_id2 fab_id<7:4> revision <3:0> addr name AS3709 C 42 ams datasheet, confidential: 2013-aug [1-02] register description detailed register description figure 53: sd1voltage register (address 00h) figure 54: sd2voltage register (address 01h) addr: 00h sd1voltage bit bit name default access bit description 7 sd1_frequ 0 rw selects between high and low frequency dependent on sd1_fsel 0 : 2mhz if sd1_fsel=0, 3mhz if sd1_fsel=1 1 : 3mhz if sd1_fsel=0, 4mhz if sd1_fsel=1 6:0 sd1_vsel 'b0000000 rw the voltage select bits set the sd1 output voltage level and power the sd1 converter down. 00h : sd1 powered down 01h-40h : v_sd1=0.6v+sd1_vsel*12.5mv 41h-70h : v_sd1=1.4v+(sd1_vsel-40h)*25mv 71h-7fh : v_sd1=2.6v+(sd1_vsel-70h)*50mv addr: 01h sd2voltage bit bit name default access bit description 7 sd2_frequ 0 rw selects between high and low frequency dependent on sd2_fsel 0 : 2mhz if sd2_fsel=0, 3mhz if sd2_fsel=1 1 : 3mhz if sd2_fsel=0, 4mhz if sd2_fsel=1 6:0 sd2_vsel 'b000 0000 rw the voltage select bits set the sd2 output voltage level and power the sd2 converter down. 00h : sd2 powered down 01h-40h : v_sd2=0.6v+sd2_vsel*12.5mv 41h-70h : v_sd2=1.4v+(sd2_vsel-40h)*25mv 71h-7fh : v_sd2=2.6v+(sd2_vsel-70h)*50mv ams datasheet, confidential: 2013-aug [1-02] AS3709 C 43 register description figure 55: sd3voltage register (address 02h) figure 56: sd4voltage register (address 03h) addr: 02h sd3voltage bit bit name default access bit description 7 sd3_frequ 0 rw selects between high and low frequency dependent on sd3_fsel 0 : 2mhz if sd3_fsel=0, 3mhz if sd3_fsel=1 1 : 3mhz if sd3_fsel=0, 4mhz if sd3_fsel=1 6:0 sd3_vsel 'b000 0000 rw the voltage select bits set the sd3 output voltage level and power the sd3 converter down. 00h : sd3 powered down 01h-40h : v_sd3=0.6v+sd3_vsel*12.5mv 41h-70h : v_sd3=1.4v+(sd3_vsel-40h)*25mv 71h-7fh : v_sd3=2.6v+(sd3_vsel-70h)*50mv addr: 03h sd4voltage bit bit name default access bit description 7 sd4_frequ 0 rw selects between high and low frequency dependent on sd4_fsel 0 : 2mhz if sd3_fsel=0, 3mhz if sd3_fsel=1 1 : 3mhz if sd3_fsel=0, 4mhz if sd3_fsel=1 6:0 sd4_vsel 'b000 0000 rw the voltage select bits set the sd4 output voltage level and power the sd4 converter down. 00h : sd4 powered down 01h-40h : v_sd4=0.6v+sd4_vsel*12.5mv 41h-70h : v_sd4=1.4v+(sd4_vsel-40h)*25mv 71h-7fh : v_sd4=2.6v+(sd4_vsel-70h)*50mv AS3709 C 44 ams datasheet, confidential: 2013-aug [1-02] register description figure 57: sd5voltage register (address 04h) figure 58: ldo1voltage register (address 05h) figure 59: ldo2voltage register (address 06h) addr: 04h sd5voltage bit bit name default access bit description 7 sd5_frequ 0 rw selects between high and low frequency dependent on sd5_fsel 0 : 2mhz if sd3_fsel=0, 3mhz if sd3_fsel=1 1 : 3mhz if sd3_fsel=0, 4mhz if sd3_fsel=1 6:0 sd5_vsel 'b000 0000 rw the voltage select bits set the sd5 output voltage level and power the sd5 converter down. 00h : sd5 powered down 01h-40h : v_sd4=0.6v+sd4_vsel*12.5mv 41h-70h : v_sd4=1.4v+(sd4_vsel-40h)*25mv 71h-7fh : v_sd4=2.6v+(sd4_vsel-70h)*50mv addr: 05h ldo1voltage bit bit name default access bit description 7 ldo1_ilimit 0 rw sets limit of ldo1 ? 0 :? 150ma operating range ? 1 : ?300ma operating range 6:0 ldo1_vsel 'b00 0000 rw the voltage select bits set the ldo1 output voltage 0.825v...3.3v, 25mv steps ? 00h : ?ldo1 off ? 01h-24h : ?v_ldo1=0.8v+ldo1_vsel*25mv ? 25h-3fh : ?do not use ? 40h-7fh : v_ldo1=1.725v+(ldo 1_vsel-40h)*25mv addr: 06h ldo2voltage bit bit name default access bit description 7 ldo2_ilimit 0 rw sets limit of ldo2 ? 0 :? 150ma operating range ? 1 : ?300ma operating range 8:0 ldo2_vsel 'b00 0000 rw the voltage select bits set the ldo2 output voltage 0.825v...3.3v, 25mv steps ? 00h : ?ldo2 off ? 01h-24h : ?v_ldo2=0.8v+ldo2_vsel*25mv ? 25h-3fh : ?do not use ? 40h-7fh : v_ldo2=1.725v+(ldo2_vsel-40h)*25mv ams datasheet, confidential: 2013-aug [1-02] AS3709 C 45 register description figure 60: gpio1control register (address 0ch) addr: 0ch gpio1control bit bit name default access bit description 7gpio1_invert 0 rw invert gpio1 input/output ? 0 : ?normal mode ? 1 : ?invert input or output 6:3 gpio1_iosf 'b0000 rw select the gpio1 special function ? . 0 : ?normal i/o operation ? . 1 : ?interrupt output ? . 2 : ?vsup_low output ? . 3 : ?gpio interrupt input ? . 4 : ?na ? . 5 : ? vselect input, (apply on reg1_select and reg2_select, if gpio2_iosf =5 then apply on reg1_select only) ? . 6 : ?standby + vselect + restart interrupt input ? . 7 : ?pwr_good output ? . 8 : ?na ? . 9 : ?na ? 10 : ?na ? 11 : ?na ? 12 : ?na ? 13 : ?na ? 14 : ?na ? 15 : ?na 2:0 gpio1_mode 'b011 rw selects the gpio1 mode (i, i/o, tri, pulls) ? 0 : ?input ? 1 : ?output (push and pull) ? 2 : ?io (open drain, only nmos is active) ? 3 : ?na ? 4 : ?input with pullup ? 5 : ?input with pulldown ? 6 : ?io (open drain (nmos) with pullup) ? 7 : ?na AS3709 C 46 ams datasheet, confidential: 2013-aug [1-02] register description figure 61: gpio2control register (address 0dh) addr: 0dh gpio2control bit bit name default access bit description 7gpio2_invert 0 rw invert gpio2 input/output ? 0 : ?normal mode ? 1 : ?invert input or output 6:3 gpio2_iosf 'b0000 rw select the gpio2 special function ? . 0 : ?normal i/o operation ? . 1 : ?interrupt output ? . 2 : ?vsup_low output ? . 3 : ?gpio interrupt input ? . 4 : ?na ? . 5 : ?vselect input, (apply on reg1_select and reg2_select, if gpio1_iosf=5 then apply on reg2_select only) ? . 6 :? standby + vselect + restart interrupt input ? . 7 : ?pwr_good output ? . 8 : ?na ? . 9 : ?na ? 10 : ?na ? 11 : ?na ? 12 : ?na ? 13 : ?na ? 14 : ?na ? 15 : ?na 2:0 gpio2_mode 'b011 rw selects the gpio2 mode (i, i/o, tri, pulls) ? 0 :? input ? 1 :? output (push and pull) ? 2 : ?io (open drain, only nmos is active) ? 3 : ?na ? 4 : ?input with pullup ? 5 : ?input with pulldown ? 6 : ?io (open drain (nmos) with pullup) ? 7 : ?na ams datasheet, confidential: 2013-aug [1-02] AS3709 C 47 register description figure 62: sdcontrol register (address 10h) figure 63: gpiosignal_out register (address 20h) addr: 10h sdcontrol bit bit name default access bit description 7- 'b0n/ado not use 6 ldo2_enable 'b1 rw global ldo2 enable ? 0 : ?ldo2 off ? 1 : ?ldo2 on 5 ldo1_enable 'b1 rw global ldo1 enable ? 0 : ?ldo1 off ? 1 : ?ldo1 on 4 sd5_enable 'b1 rw global stepdown5 enable ? 0 : ?sd off ? 1 : ?sd on 3 sd4_enable 'b1 rw global stepdown4 enable ? 0 : ?sd off ? 1 :? sd on 2 sd3_enable 'b1 rw global stepdown3 enable ? 0 : ?sd off ? 1 :? sd on 1 sd2_enable 'b1 rw global stepdown2 enable ? 0 : ?sd off ? 1 : ?sd on 0 sd1_enable 'b1 rw global stepdown1 enable ? 0 : ?sd off ? 1 : ?sd on addr: 20h gpiosignal_out bit bit name default access bit description 7:2 - 'b0000 n/a do not use 1gpio2_out 0 rw this bit determines the output signal of the gpio2 pin when selected as output source. 0gpio1_out 0 rw this bit determines the output signal of the gpio1 pin when selected as output source. AS3709 C 48 ams datasheet, confidential: 2013-aug [1-02] register description figure 64: gpiosignal_in register (address 21h) figure 65: reg1_voltage register (address 22h) figure 66: reg2_voltage register (address 23h) addr: 21h gpiosignal_in bit bit name default access bit description 7:2 - 'b0000 n/a do not use 1gpio2_in 0 ro this bit reflects the logic level of the gpio2 pin when configured as digital input pin. 0gpio1_in 0 ro this bit reflects the logic level of the gpio1 pin when configured as digital input pin. addr: 22h reg1_voltage bit bit name default access bit description 7:0 reg1_voltage 'b0000 0000 rw this register is mapped to the register address 0h+reg1_select , if giox_iosf = 5 or 6 (vselect input), and input = 1. this feature allows voltage switching of a predefined regulator with just one gpio input. ? 0 ..ffh :? selects voltage and frequency bits of dcdc addr: 23h reg2_voltage bit bit name default access bit description 7:0 reg2_voltage 'b0000 0000 rw this register is mapped to the register address 0h+reg1_select, if giox_iosf=5 or 6 (vselect input), and input = 1, this feature allows voltage switching of a predefined regulator with just one gpio input ? 0 ..ffh :? selects voltage and frequency bits of dcdc ams datasheet, confidential: 2013-aug [1-02] AS3709 C 49 register description figure 67: reg_control register (address 24h) figure 68: gpioctrl_sd register (address 25h) addr: 24h reg_control bit bit name default access bit description 7:4 reg2_select 'b1111 rw selects regulator for mapping feature; if reg_select2 0ch, then feature is disabled. 3:0 reg1_select 'b1111 rw selects regulator for mapping feature; if reg_select1 0ch, then feature is disabled. addr: 25h gpioctrl_sd bit bit name default access bit description 7:6 gpio_ctrl_sd4 'b00 rw enable gpio control of dcdc sd4. gpio ctrl only enabled, if sd4_vsel > 0 ? 0 : ?no gpio control ? 1 : ?controlled by gpio1 ? 2 : ?controlled by gpio2 ? 3 :? na 5:4 gpio_ctrl_sd3 'b00 rw enable gpio control of dcdc sd3. gpio ctrl only enabled, if sd3_vsel > 0 ? 0 : ?no gpio control ? 1 : ?controlled by gpio1 ? 2 : ?controlled by gpio2 ? 3 : ?na 3:2 gpio_ctrl_sd2 'b00 rw enable gpio control of dcdc sd2. gpio ctrl only enabled, if sd2_vsel > 0 ? 0 : ?no gpio control ? 1 : ?controlled by gpio1 ? 2 :? controlled by gpio2 ? 3 : ?na 1:0 gpio_ctrl_sd1 'b00 rw enable gpio control of dcdc sd1. gpio ctrl only enabled, if sd1_vsel > 0 ? 0 : ?no gpio control ? 1 : ?controlled by gpio1 ? 2 : ?controlled by gpio2 ? 3 : ?na AS3709 C 50 ams datasheet, confidential: 2013-aug [1-02] register description figure 69: gpioctrl_ldo register (address 26h) addr: 26h gpioctrl_ldo bit bit name default access bit description 7:6 - 'b00 n/a - 5:4 gpio_ctrl_ldo2 'b00 rw enable gpio control of ldo2. gpio ctrl only enabled, if ldo2_vsel > 0 0 :? no gpio control ? 1 :? controlled by gpio1 ? 2 :? controlled by gpio2 ? 3 : ?na 3:2 gpio_ctrl_ldo1 'b00 rw enable gpio control of ldo1. gpio ctrl only enabled, if ldo1_vsel > 0 0 : no gpio control ? 1 : ?controlled by gpio1 ? 2 : ?controlled by gpio2 ? 3 : ?na 1:0 gpio_ctrl_sd5 'b00 rw enable gpio control of sd5. gpio ctrl only enabled, if sd5_vsel > 0 ? 0 : ?no gpio control ? 1 :? controlled by gpio1 ? 2 : ?controlled by gpio2 ? 3 :? na ams datasheet, confidential: 2013-aug [1-02] AS3709 C 51 register description figure 70: sd_control3 register (address 29h) addr: 29h sd_control3 bit bit name default access bit description 7 sd5_slave 0 rw enables slave mode of sd5 0 : ?normal mode of sd5 ? 1 :? sd5 is slave of sd3 7 sd4_slave 0 rw enables slave mode of sd4 0 : ?normal mode of sd4 ? 1 : ?sd4 is slave of sd3 5 sd2_slave 0 rw enables slave mode of sd2 ? 0 : ?normal mode of sd2 ? 1 : ?sd2 is slave of sd1 4sd5_fsel 0 rw selects between high and low frequency range ? 0 :? 2 or 3mhz frequency (selectable by sd5_frequ) ? 1 : ?3 or 4mhz frequency (selectable by sd5_frequ) 3sd5_fast 0 rw selects a faster regulation mode for sd5 suitable for larger load changes. ? 0 : ?normal mode, cext=10f ? 1 :? fast mode, cext=22f required 2 sd5_low_noise 0 rw enables low noise mode of sd5. if enabled smaller current pulses and output ripple is activated. ? 0 : ?normal mode. minimum current pulses of >100ma applied in skip mode. ? 1 :? low noise mode. only minimum on time applied in skip mode. 1:0 - 'b00 n/a - AS3709 C 52 ams datasheet, confidential: 2013-aug [1-02] register description figure 71: sd_control1 register (address 30h) addr: 30h sd_control1 bit bit name default access bit description 7 sd4_low_noise 0 rw enables low noise mode of sd4. if enabled smaller current pulses and output ripple is activated. ? 0 : ?normal mode. minimum current pulses of >100ma applied in skip mode. ? 1 :? low noise mode. only minimum on time applied in skip mode. 6 sd3_low_noise 0 rw enables low noise mode of sd3. if enabled smaller current pulses and output ripple is activated. ? 0 :? normal mode. minimum current pulses of >100ma applied in skip mode. ? 1 : ?low noise mode. only minimum on time applied in skip mode. 5 sd2_low_noise 0 rw enables low noise mode of sd2. if enabled smaller current pulses and output ripple is activated. ? 0 : ?normal mode. minimum current pulses of >100ma applied in skip mode. ? 1 : ?low noise mode. only minimum on time applied in skip mode. 4 sd1_low_noise 0 rw enables low noise mode of sd1. if enabled smaller current pulses and output ripple is activated. ? 0 : ?normal mode. minimum current pulses of >100ma applied in skip mode. ? 1 : ?low noise mode. only minimum on time applied in skip mode. 3sd4_fast 0 rw selects a faster regulation mode for sd4 suitable for larger load changes. ? 0 : ?normal mode, cext=10f ? 1 : ?fast mode, cext=22f required 2sd3_fast 0 rw selects a faster regulation mode for sd3 suitable for larger load changes. ? 0 : ?normal mode, cext=10f ? 1 :? fast mode, cext=22f required 1sd2_fast 0 rw selects a faster regulation mode for sd2 suitable for larger load changes. ? 0 : ?normal mode, cext=10f ? 1 : ?fast mode, cext=22f required 0sd1_fast 0 rw selects a faster regulation mode for sd1 suitable for larger load changes. ? 0 :? normal mode, cext=10f ? 1 :? fast mode, cext=22f required ams datasheet, confidential: 2013-aug [1-02] AS3709 C 53 register description figure 72: sd_control2 register (address 31h) addr: 31h sd_control2 bit bit name default access bit description 7:6 sd_dvm_select 'b00 rw apply dvm counter to the following dcdc converter 0 :? select sd1 for dvm ? 1 : ?select sd2 for dvm ? 2 : ?select sd3 for dvm ? 3 :? select sd5 for dvm 5:4 dvm_time 'b00 rw time steps of dvm voltage change of selected step down, if voltage of step down is changed during operation (sdx_vsel) voltage is decreased/increased by single steps 12.5mv ? 0 : ?0 sec, immediate change (no dvm) ? 1 :? 4 sec time delay between steps ? 2 : ?8 sec time delay between steps ? 3 : ?16 sec time delay between steps 3sd4_fsel 0 rw selects between high and low frequency range ? 0 :? 2 or 3mhz frequency (selectable by sd4_frequ) ? 1 : ?3 or 4mhz frequency (selectable by sd4_frequ) 2sd3_fsel 0 rw selects between high and low frequency range ? 0 :? 2 or 3mhz frequency (selectable by sd3_frequ) ? 1 :? 3 or 4mhz frequency (selectable by sd3_frequ) 1sd2_fsel 0 rw selects between high and low frequency range ? 0 :? 2 or 3mhz frequency (selectable by sd2_frequ) ? 1 : ?3 or 4mhz frequency (selectable by sd2_frequ) 0sd1_fsel 0 rw selects between high and low frequency range ? 0 :? 2 or 3mhz frequency (selectable by sd1_frequ) ? 1 : ?3 or 4mhz frequency (selectable by sd1_frequ) AS3709 C 54 ams datasheet, confidential: 2013-aug [1-02] register description figure 73: supply_voltage_monitor register (address 32h) addr: 32h supply_voltage_monitor bit bit name default access bit description 7fastresen 0 rw ? 0 : ?resvoltfall debounce time = 3msec ? 1 : ?resvoltfall debounce time = 4sec (tbd) 6supresen 0 rw ? 0 : ?a reset is generated if v sup falls below 2.7v ** ? 1 : ?a reset is generated if v sup falls below resvoltfall ** if v sup falls below resvoltfall only an interrupt is generated (if enabled) and the processor can shut down the system 5:3 resvoltfall 'b000 rw this value determines the reset level resvoltfall for falling v sup . it is recommended to set this value at least 200mv lower than resvoltrise (the levels differ between 3.3v and 5v supply) ? 0 : ?2.7v / 3.6v ? 1 :? 2.8v / 3.7v ? 2 : ?2.9v / 3.8v ? 3 : ?3.0v / 3.9v ? 4 : ?3.1v / 4.0v ? 5 : ?3.2v / 4.1v ? 6 :? 3.3v / 4.2v ? 7 : ?3.4v / 4.4v 2:0 resvoltrise 'b000 ro (otp) this value determines the reset level resvoltrise for rising v sup . it is recommended to set this value at least 200mv higher than resvoltfall (the levels differ between 3.3v and 5v supply) ? 0 : ?2.7v / 3.6v ? 1 :? 2.8v / 3.7v ? 2 : ?2.9v / 3.8v ? 3 : ?3.0v / 3.9v ? 4 : ?3.1v / 4.0v ? 5 : ?3.2v / 4.1v ? 6 : ?3.3v / 4.2v ? 7 : ?3.4v / 4.4v ams datasheet, confidential: 2013-aug [1-02] AS3709 C 55 register description figure 74: startup_control register (address 33h) addr: 33h startup_control bit bit name default access bit description 7:2 - b000 0000 n/a do not use 1 reslevel_5v 0 rw selects the 5v supply reset level (see resvoltrise and resvoltfall) 0 : ?3.3v level 1 :? 5.0v level 0 power_off_ at_vsuplow 0rw switch on power off mode if low v sup is detected during active or standby mode (pin on= low and bit auto_off=0) 0 :? if low v sup is detected, v sup is continuously monitored and chip startup initiated if v sup is above resvoltrise 1 :? if low v sup is detected, enter power off mode AS3709 C 56 ams datasheet, confidential: 2013-aug [1-02] register description figure 75: resettimer register (address 34h) addr: 34h resettimer bit bit name default access bit description 7- 'b0n/ado not use 6 stby_reset_disa ble 0rw disable reset output signal (pin xres) in standby mode. ? 0 : ?normal mode, reset is active in standby mode ? 1 : ?no reset in standby mode and during exit of stand-by mode 5auto_off 0 ro defines startup behavior at first v sup connection 0 :? startup of chip if v sup >resvoltrise 1 : ?enter power off mode (startup with on key) 4:3 off_delay 'b01 rw set delay between i2c command, gpio or reset signal for power_off, standby mode or reset and execution of that command. ? 0 : ?no delay ? 1 :? 8 msec ? 2 : ?16 msec ? 3 : ?32 msec 2:0 res_timer 'b000 rw set reset time, after the last regulator has started ? 0 : ?restime = 2ms ? 1 :? restime = 4ms ? 2 : ?restime = 8ms ? 3 : ?restime = 16ms 4 :? restime = 32ms 5 : ?restime = 64ms 6 : ?restime = 128ms 7 : ?restime = 160ms ams datasheet, confidential: 2013-aug [1-02] AS3709 C 57 register description figure 76: referencecontrol register (address 35h) addr: 35h referencecontrol bit bit name default access bit description 7on_reset_delay 0 rw sets the on reset delay time ? 0 :? 8 sec (if onkey_reset=1) ? 1 :? 4 sec (if onkey_reset=1) 6- 0rw- 5 clk_div2 0 rw divide internal clock oscillator by 2 to reduce quiescent current for low power operation ? 0 : ?normal mode ? 1 :? internal clock frequency divided by two. all timings are increased by two. switching frequency of all dcdc converters are divided by two. reduced transient performance of dcdc converters. 4 standby_mode _on 0rw setting to 1 sets the pmu into standby mode. all regulators are disabled except those regulators enabled by register reg standby mode. xres will be pulled to low. a normal startup of all regulators will be done with any interrupt (has to be enabled before entering standby mode). during this startup, regulators defined by reg standby mode register are continuously on. 3:1 clk_int 'b000 rw sets the internal clk frequency f clk used for fuel gauge, dcdcs, pwm, ... ? 0 : ?4 mhz (default) ? 1 : ?3.8 mhz ? 2 : ?3.6 mhz ? 3 :? 3.4 mhz ? 4 : ?3.2 mhz ? 5 :? 3.0 mhz ? 6 : ?2.8 mhz ? 7 :? 2.6 mhz all frequencies, timings and delays in this datasheet are based on 4mhz clk_int 0 low_power_on 0 rw enable low power mode of internal reference. ? 0 :? standard mode ? 1 : ?low power mode - all specification except noise parameters are still valid. iq reduced by approx. 30a AS3709 C 58 ams datasheet, confidential: 2013-aug [1-02] register description figure 77: resetcontrol register (address 36h) addr: 36h resetcontrol bit bit name default access bit description 7 onkey_reset 0 rw ? 0 :? reset after 4/8 seconds on pressed disabled ? 1 : ?reset after 4/8 seconds on pressed enabled 6:3 reset_reason 'b0000 rw flags to indicate to the software the reason for the last reset ? . 0 :? v por has been reached (v sup connection from scratch) ? . 1 :? resvoltfall was reached (v sup drop below 2.75v) ? . 2 :? software forced by force_reset ? . 3 : ?software forced by power_off and on was pulled high ? . 4 :? software forced by power_off and charger was detected ? . 5 :? external triggered through the pin xres ? . 6 : ?reset caused by overtemperature t140 ? . 7 :? na ? . 8 :? reset caused by 4/8 seconds on press ? . 9 :? na ? 10 : ?na ? 11 : ?reset caused by interrupt in standby mode ? 12 : ?reset caused by on pulled high in standby mode 2 on_input 0 r_push read: this flag represents the state of the on pad directly write: setting to 1 resets the 4/8 sec. onkey_reset timer 1 power_off 0 rw setting to 1 starts a reset cycle, but waits after the reg_off state for a falling edge on the pin on 0 force_reset 0 rw setting to 1 starts a complete reset cycle ams datasheet, confidential: 2013-aug [1-02] AS3709 C 59 register description figure 78: overtemperaturecontrol register (address 37h) figure 79: reg_standby_mod1 register (address 39h) addr: 37h overtemperaturecontrol bit bit name default access bit description 7:4 - 'b0000 n/a do not use 3 rst_ov_temp_1 40 0rwp if the over-temperature thre shold 2 has been reached, the flag ov_temp_140 is set and a reset cycle is started. ov_temp_140 should be reset by writing 1 and afterward 0 to rst_ov_temp_140. 2 ov_temp_140 0 ro flag that the over-temperatu re threshold 2 (t140) has been reached - this flag is not reset by an over-temperature caused reset and has to be reset by rst_ov_temp_140 . 1 ov_temp_110 0 ro flag that the over-temperatu re threshold 1 (t110) has been reached 0 temp_pmc_on 1 ro switch on / off the temperatu re supervision; default: on - all other bits are only valid if set to 1 leave at 1, do not disable addr: 39h reg_standby_mod1 bit bit name default access bit description 7 disable_regpd 0 rw this bit disables the pulldown of all regulators ? 0 : ?normal operation approx. 1k pulldown of all regulators ? 1 : ?pulldown disabled >100k of all regulators 6ldo2_stby_on 0 rwenable ldo2 in standby mode 5ldo1_stby_on 0 rwenable ldo1 in standby mode 4 sd5_stby_on 0 rw enable step down 4 in standby mode 3 sd4_stby_on 0 rw enable step down 4 in standby mode 2 sd3_stby_on 0 rw enable step down 3 in standby mode 1 sd2_stby_on 0 rw enable step down 2 in standby mode 0 sd1_stby_on 0 rw enable step down 1 in standby mode AS3709 C 60 ams datasheet, confidential: 2013-aug [1-02] register description figure 80: regstatus register (address 73h) figure 81: interruptmask1 register (address 74h) addr: 73h regstatus bit bit name default access bit description 7:5 - b000 n/a do not use 4sd5_lv 0 ro bit is set when voltage of sd5 drops below low voltage threshold (-5%) (1msec debounce time default) 3sd4_lv 0 ro bit is set when voltage of sd4 drops below low voltage threshold (-5%) (1msec debounce time default) 2sd3_lv 0 ro bit is set when voltage of sd3 drops below low voltage threshold (-5%) (1msec debounce time default) 1sd2_lv 0 ro bit is set when voltage of sd2 drops below low voltage threshold (-5%) (1msec debounce time default) 0sd1_lv 0 ro bit is set when voltage of sd1 drops below low voltage threshold (-5%) (1msec debounce time default) addr: 74h interruptmask1 bit bit name default access bit description 7 lowvsup_int_m 1 rw set to 0 to enable the interrupt 6 ovtmp_int_m 1 rw set to 0 to enable the interrupt 5 onkey_int_m 1 rw set to 0 to enable the interrupt 4 sd5_lv_int_m 1 rw set to 0 to enable the interrupt 3 sd4_lv_int_m 1 rw set to 0 to enable the interrupt 2 sd3_lv_int_m 1 rw set to 0 to enable the interrupt 1 sd2_lv_int_m 1 rw set to 0 to enable the interrupt 0 sd1_lv_int_m 1 rw set to 0 to enable the interrupt ams datasheet, confidential: 2013-aug [1-02] AS3709 C 61 register description figure 82: interruptmask2 register (address 75h) figure 83: interruptstatus1 register (address 77h) figure 84: interruptstatus2 register (address 78h) addr: 75h interruptmask2 bit bit name default access bit description 7:2 - b0000 00 n/a do not use 1 gpio_restart_int_m 1 rw set to 0 to enable the interrupt 0 gpio_int_m 1 rw set to 0 to enable the interrupt addr: 77h interruptstatus1 bit bit name default access bit description 7 lowbat_int_i 0 pop bit is set when v sup drops below vres_fall rising edge only 6 ovtmp_int_i 0 pop bit is set when 110deg is exceeded rising edge only 5 onkey_int_i 0 pop rising and falling edge 4 sd5_lv_int_i 0 pop rising edge only 3 sd4_lv_int_i 0 pop rising edge only 2 sd3_lv_int_i 0 pop rising edge only 1 sd2_lv_int_i 0 pop rising edge only 0 sd1_lv_int_i 0 pop rising edge only addr: 78h interruptstatus2 bit bit name default access bit description 7:2 - b0000 00 n/a do not use 1 gpio_restart_int_i 0 pop falling edge 0 gpio_int_i 0 pop rising and falling edge AS3709 C 62 ams datasheet, confidential: 2013-aug [1-02] register description figure 85: asic_id1 register (address 90h) figure 86: asic_id2 register (address 91h) addr: 90h asic_id1 bit bit name default access bit description 7:0 id1 b10001110 ro - addr: 91h asic_id2 bit bit name default access bit description 3:0 revision b0010 ro note: metal fuse!!! ams datasheet, confidential: 2013-aug [1-02] AS3709 C 63 application information figure 87: application schematic application information ldo1 13 vin_ldo1 14 fb_sd2 15 gndsense 30 fb_sd5 31 pvss_sd5 32 vin_ldo2 11 fb_sd3 10 ldo2 12 vsup_sd3 7 fb_sd4 6 lx_sd3 8 pvss_sd4 5 vsup_sd5 2 vsup_sd4 3 lx_sd4 4 sclk 24 sda 25 vsup_sd1 22 lx_sd1 21 gpio2 28 xres 27 on 26 vsup_sd2 18 fb_sd1 19 lx_sd2 17 pvss_sd2 16 ldos dcdc sd 1-5 logic & control AS3709 upmic ep_vss 33 gpio1 29 lx_sd5 1 pvss_sd3 9 pvss_sd1 20 v2_5 23 AS3709 2.2f 2.2f 2.2f 2.2f 2.2f 2.2f 2.2f 2.2f 2.2f 10f 10f 10f 10f 10f gnd gnd gnd gnd vsup vsup 1h 1h 1h 1h 1h gnd gnd vsup gnd gnd gnd gnd vsup vsup vsup vsup gnd gnd gnd gnd gnd 1f gnd sclk sda xres gpio1 gpio2 8k2 8k2 vsup 401-1426-1-nd kmr211glfs 401-1426-1-nd kmr211glfs 1m 1m 10k gnd v2_5 v2_5 vsup gnd on sd1 sd2 sd3 sd4 sd5 ldo1 ldo2 AS3709 C 64 ams datasheet, confidential: 2013-aug [1-02] application information figure 88: layout guidelines 1/2 layout guidelines 1/2: this figure shows the recommended layout and placement of the external components for the 5 x 1a application circuit. red line s and areas are connections on top layer. grey lines and areas are gnd and pvss connections on top layer. light blue lines and areas are connec tions on an inner layer or bottom layer. black round dots are vias. vsup areas should be connected to an inner vsup plane via vias. gnd and pvss areas should be connect ed to an inner gnd plane via vias. a 1 3 5 7 AS3709 qfn 32-pin 4x4mm exposed pad: gnd 24 22 20 18 23 21 19 17 2 4 6 8 28 27 26 25 32 31 30 29 12 11 10 9 16 15 14 13 33 v 2 _ 5 s c l k vssa gpio1 gpio2 xres on sda v sup _ sd5 vs u p _ s d 4 lx_sd4 pvss_sd4 vsup_sd3 lx_sd3 pvss _ s d3 fb_sd3 vin_ldo2 ldo2 ldo1 vin_ldo1 fb_sd2 lx_sd2 vsup_sd2 fb_sd1 pvss_sd1 fb_sd5 pvss_sd5 fb_sd3 fb_sd4 fb_sd2 fb_sd1 l5 l4 l3 l1 l2 c out_sd5 c out_sd4 c out_sd3 c out_sd1 c out_sd2 c in_sd5 c in_sd4 c in_sd3 c in_sd1 cin_sd2 c in_ldo2 c out_ldo2 c out_ldo1 c in_ldo1 l x _ s d5 lx_sd1 lx_sd2 p v s s_ s d 2 sd5 sd4 sd3 sd2 sd1 fb_sd4 fb_sd2 ams datasheet, confidential: 2013-aug [1-02] AS3709 C 65 application information pcb with minimum 4 layers is recommended. figure 89: layout guidelines 2/2 layout guidelines 2/2: layout guidelines 2/2: this figure shows the recommended layout and placement of the external components for the 1 x 2a & 1 x 3a application circuit. red lines and areas are connections on top layer. grey lines and areas are gnd and pvss connections on top layer. ligh t blue lines and areas are connections on an inner layer or bottom layer. black roun d dots are vias. vsup areas should be conn ected to an inner vsup plane via vias. gnd and pvss areas should be connected to an inner gnd plane via vias. a pcb wi th minimum 4 layers is recommended. 1 3 5 7 AS3709 qfn 32-pin 4x4mm exposed pad: gnd 24 22 20 18 23 21 19 17 2 4 6 8 28 27 26 25 32 31 30 29 12 11 10 9 16 15 14 13 33 v 2 _ 5 s c l k vssa gpio1 gpio2 xres on sda lx_sd5 lx_sd4 vsup_sd3 lx_sd3 p v s s_sd 3 vin_ldo2 ldo2 ldo1 vin_ldo1 p vs s _ s d2 vsup_sd2 fb_sd1 pvss_sd1 lx_sd1 p v s s _sd5 fb_sd3 lx_sd2 pvss_sd4 sd3 & sd4 & sd5 sd1 & sd1 vsup sd4+sd5 c in_sd1 c out_sd1/2 c out_sd1/2 c in_sd2 c in_ldo2 c out_ldo2 c out_ldo1 c in_ldo1 l1 l3 c out_sd3/4/5 c out_sd3/4/5 c out_sd3/4/5 c in_sd5 c in_sd4 c in_sd3 vsup_sd1 lx_sd1 fb_sd1 fb_sd3 AS3709 C 66 ams datasheet, confidential: 2013-aug [1-02] package drawings & markings figure 90: qfn32 4x4 0.4mm pitch package drawing note(s) and/or footnote(s): 1. dimensioning and tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. dimension b applies to metallized term inal and is measured between 0.25mm and 0.30mm from terminal tip. dimension l1 represents terminal full back from package edge up to 0.15mm is acceptable. 4. coplanarity applies to the exposed heat slug as well as the terminal. 5. radius on terminal is optional. 6. n is the total number of terminals. package drawings & markings ref. min nom max a 0.80 0.90 1.00 a1 0 0.02 0.05 a3 0.20 ref l 0.35 0.40 0.45 l1 0 - 0.15 b 0.15 0.20 0.25 d4.00 bsc e4.00 bsc e0.40 bsc d2 2.60 2.70 2.80 e2 2.60 2.70 2.80 aaa - 0.10 - bbb - 0.07 - ccc - 0.10 - ddd - 0.05 - eee - 0.08 - fff - 0.10 - n32 ams datasheet, confidential: 2013-aug [1-02] AS3709 C 67 package drawings & markings figure 91: wlp36 0.4mm pitch package drawing note(s) and/or footnote(s): 1. pin 1 = a1 2. ccc coplanarity 3. a1 dimensions are in m AS3709 C 68 ams datasheet, confidential: 2013-aug [1-02] package drawings & markings figure 92: qfn marking qfn marking: shows the package marking of the qfn product version. figure 93: qfn package code figure 94: start-up revision code figure 95: wl-csp marking yy ww x zz year manufacturing week plant identifier free choice revision code sequence k2v0-es engineering samples, no sequence programmed or sequence programmed on request k2v0-00 standard programming (no sequence programmed) k2v0-xx customer specified sequence programmed during production test AS3709 k2v0-xx yywwxzz AS3709 xxxx AS3709 k2v0-xx xxxx ams datasheet, confidential: 2013-aug [1-02] AS3709 C 69 package drawings & markings figure 96: wl-csp code figure 97: start-up revision code xxxx encoded datecode revision code sequence k2v0-es engineering samples, no sequence programmed or sequence programmed on request empty standard programming (no sequence programmed) k2v0-00 standard programming (no sequence programmed) k2v0-xx customer specified sequence programmed during production test AS3709 C 70 ams datasheet, confidential: 2013-aug [1-02] rohs compliant & ams green statement rohs: the term rohs compliant means that ams products fully comply with current rohs directive. our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, rohs compliant products are suitable for use in specif ied lead-free processes. ams green (rohs compliant and no sb/br): ams green defines that additionally to rohs compliance, our products are free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material). important information: the information provided in this statement represents ams knowledge and belief as of the date that it is provided. ams bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are unde rway to better integrate information from third parties. ams has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams and ams suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. rohs compliant & ams green statement ams datasheet, confidential: 2013-aug [1-02] AS3709 C 71 ordering & contact information figure 98: ordering information note: on request. buy our products or get free samples online at: www.ams.com/icdirect technical support is available at: www.ams.com/technical-support for further information and requests, e-mail us at: ams_sales@ams.com for sales offices, distributors and representatives, please visit: www.ams.com/contact headquarters ams ag tobelbaderstrasse 30 8141 unterpremstaetten austria, europe tel: +43 (0) 3136 500 0 website: www.ams.com ordering code marking sequence description delivery form package AS3709- bqfr-es k2v0-es sequence programmable on request pmic with 5 dcdc and 2 ldos tray 32-pin qfn 4x4 AS3709- bqfm-00 k2v0-00 default sequence pmic with 5 dcdc and 2 ldos tape & reel 32-pin qfn 4x4 AS3709- bqfm-xx k2v0-xx customer specified sequence pmic with 5 dcdc and 2 ldos tape & reel 32-pin qfn 4x4 AS3709- bwlr-es (note:) k2v0-es sequence programmable on request pmic with 5 dcdc and 2 ldos tray 36-pin wl-csp 0.4mm pitch AS3709- bwlt-xx (note:) k2v0-xx customer specified sequence pmic with 5 dcdc and 2 ldos tape & reel 36-pin wl-csp 0.4mm pitch ordering & contact information AS3709 C 72 ams datasheet, confidential: 2013-aug [1-02] copyrights & disclaimer copyright ams ag, tobelbader strasse 30, 8141 unterpremstaetten, austria-europe. trademarks registered. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. devices sold by ams ag are covered by the warranty and patent indemnification provisions appear ing in its term of sale. ams ag makes no warranty, express, statutory, implied, or by description regarding the inform ation set forth herein. ams ag reserves the right to change specifications and prices at any time and without notice. theref ore, prior to designing this product into a system, it is necessary to check with ams ag for current information. this product is intended for use in commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams ag for each application. this product is provided by ams as is and any express or implied warranties, including, but not limited to the implied warranties of merc hantability and fitness for a particular purpose are disclaimed. ams ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any th ird party shall arise or flow out of ams ag rendering of technical or other services. copyrights & disclaimer ams datasheet, confidential: 2013-aug [1-02] AS3709 C 73 reference guide 1 general description 1 key benefits & features 2 applications 2 block diagram 3 pin assignment 6absolute maximum ratings 8 electrical characteristics 9 detailed description - power management functions 9 step down dcdc converter 10 mode settings 10 low-ripple, low-noise operation 10 high-efficiency operat ion (default setting) 11 low power mode operation (automatically controlled) 11 dvm (dynamic voltage management) 12 fast regulation mode 12 selectable frequency operation 12 100% pmos on mode for low dropout regulation 12 step down converter configuration modes 15 parameters 21 universal io ldo regulators 22 parameter 23 low power ldo v2_5 regulator 23 parameter 24 detailed description - system functions 24 start-up 24 normal start-up 24 parameter 26 reset 26 reset reasons 26 voltage detection 26 power off 27 software forced reset 27 external triggered reset 27 over-temperature reset 27 long on-key press 27 parameter 29 stand-by 29 internal references 29 low power mode 30 gpio pins 31 io functions 31 normal io operation: 31 interrupt output 31 vsup_low output 31 gpio interrupt input 32 vselect input 32 stand-by and vselect input 33 pwrgood output 33 supervisor reference guide AS3709 C 74 ams datasheet, confidential: 2013-aug [1-02] reference guide 33 temperature supervision 34 interrupt generation 34 2-wire-serial control interface 34 feature list 35 i2c protocol 36 i2c write access 37 i2c read access 38 i2c parameter 40 register description 42 detailed register description 63 application information 67 package drawings & markings 71 rohs compliant & ams green statement 72 ordering & contact information 73 copyrights & disclaimer |
Price & Availability of AS3709
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |